As an emerging non-volatile memory technology, Resistive Random Access Memories (RRAMs) have great advantages in many aspects, such as, device structure, cell area, storage density, power consumption, programming/erasing speed, 3D integration and multi-value storage, and are becoming one of the most powerful competitors in replacing “flash” memories which are currently mainstream products in the non-volatile memory market. A sandwich structure of Metal/Insulator/Metal (MIM) is a basic structure for the resistive memory, and such a vertical MIM structure is beneficial for cross-array integration to achieve super high density storage. In a cross-array structure, cross points between upper and lower lines which are perpendicular to each other contain memory cells, each of which can achieve gating and reading/writing.
However, the existing resistive memory cell has a symmetric read current-voltage curve under positive and negative voltage polarities. As shown in FIG. 1, when the resistor memory cell is in a low resistance state and a range of −Vread→Vread is Direct Current (DC) scanned, this device presents a symmetric current-voltage curve under positive and negative voltage polarities. When a cross-array memory architecture is used, a memory cell in the low resistance state will provide an additional leakage path due to the symmetric read electrical characteristic of the memory cell. Such a leakage path will impact information read from a gated memory cell and cause a serious read crosstalk problem in the cross array. As shown in FIG. 2, among four neighboring memory cells, a cell at coordinates (1, 1) is in a high resistance state, and the other three cells (1, 2), (2, 2), and (2, 1) are all in a low resistance state. When a read voltage is applied to the device (1, 1), the current may flow along the low resistance path (1, 2)→(2, 2)→(2, 1) (shown by the dashed line), such that the device (1, 1) is misread as an ON state (or a low resistance state).
In the prior art, the misreading phenomenon may be effectively addressed by connecting a rectifier diode to the resistive memory cell in series. However, because the rectifier diode generally shows an ON feature only in the forward direction but cannot provide enough current in the reverse direction, the resistive memory cell that currently can be integrated with the rectifier diode must have a unipolar resistance switching feature. That is, programming and erasing operations for the resistive memory cell must be done in the same voltage polarity. For a more popular bipolar resistive memory cell, its programming and erasing operations must be done in opposite voltage polarities, and therefore a single rectifier diode cannot meet the current requirement for its erasing in the reverse direction. As a result, the misreading phenomenon caused by the read crosstalk in a cross array of bipolar resistive memory cells cannot be effectively addressed up to now.